1. Field of the Invention
The present invention generally relates to fabrication and structure of dielectric layers, and more particularly to a method and a structure for the adhesion enhancement between dielectric material and low-k material.
2. Description of the Prior Art
As device scaling continues to reduce feature size, the gain in device speed at the gate level is offset by propagation delays at metal material interconnects due to the increased RC time constant. And the propagation delay can be reduced by the incorporation of low-k (low dielectric constant) materials. The use of low-k material also lowers power consumption and reduces transistor's crosstalk.
Future technology nodes will require materials with a progressively lower dielectric constant in order to meet performance goals. Normally a dielectric constant bellow 3.7 is called low-k material. By the year 2003, the effective dielectric constant for the inter-level dielectric (ILD) will be between 2.2 and 2.9 (for technology nodes between 130 nm and 100 nm) requiring extreme low-k materials with a bulk dielectric constant as low as 2.0.
Carbide and nitride applying to the barrier layer have found the widest application in ILD layers partly because of the familiarity and varied methods for deposition carbide or nitride layers pervasive in the semiconductor manufacturing processes. Carbide/nitride as ILD layers can be deposited by any number of processes, including chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) and liquid spin-on glass forming techniques, tailored to achieving high-quality ILDs characterized by good electrical and physical properties.
A conventional approach in forming ILDs involves depositing a dielectric layer and a low-k layer. Surly, a couple of layers without low-k you can design, but ultimately you must integrate it. After depositing, the planarization is treated by a chemical-mechanical polishing (CMP), to provide a substantially flat upper surface on which additional layers are formed. And then the delamination occurs between the dielectric layer and the low-k layer. It also causes the degradation which is due to bond breaking and loss of hydrogen and/or methyl groups contained in such materials when oxygen or oxygen radicals react with the surface of the low-k layer.
An embodiment as shown in FIG. 1. Before the trench open in forming Cu damascene process: Firstly, the Cu layer 101 is formed. Next, the silicon nitride (SiN) layer 102 is formed on the Cu layer 101 for blocking Cu expansion. Then forming a low-k material, such as a carbon doped oxide (CDO) layer 103, on the silicon nitride (SiN) layer 102. Because it has a poor adhesion between silicon nitride (SiN) layer 102 and carbon doped oxide (CDO) layer 103, and the following steps may include one or more steps of chemical-mechanical polishing (CMP), other etch process or other deposition process. After these steps, the delamination easily occurs between the silicon nitride (SiN) layer 102 and the carbon doped oxide (CDO) layer 103.
Thus, there exists a need for improving adhesion between a dielectric layer and a low-k layer. The following provides a method and a structure for it.